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Why DRAM and SSD Could Become Two Primary Themes in the AI Infrastructure Cycle

FUNDA·2026年1月6日

KV cache offload from HBM to DRAM/SSD boosts MFU and cuts $/token, making memory stocks AI-cycle leaders.

Before reading this article, you may want to review our earlier reports on memory and storage.

At CES 2026, NVIDIA CEO Jensen Huang captured the data center’s central tension in a single line, shifting the bottleneck from “insufficient compute” to “insufficient context”: “Context is the new bottleneck — storage must be rearchitected.” As models grow larger, context windows extend, multi-turn interactions increase, and concurrent sessions proliferate, the key determinant of system throughput and cost is no longer just FLOPS. It is how “context data” is retained, moved, and reused.

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