Heterogeneous Integration and Chiplets: The Defining Trends from ISSCC 2026

This article is reproduced with permission from Silicon Talks. This report was written by a friend of ours, and it’s very closely aligned with our line of research. We’ll be releasing a few more deep dives on optics names soon.

New integration technologies are reshaping the compute landscape in real time. As recently as ISSCC 2020, chiplet-related papers appeared only sporadically. Fast-forward to today, and chiplet architectures have penetrated virtually every ISSCC technical track: digital, compute, memory, sensing, display, with heterogeneous integration also making inroads into Power, Bio, and RF. This year, papers on heterogeneous integration and chiplets surged in volume.

This article provides a systematic review of how chiplet and heterogeneous integration technologies evolved at ISSCC 2026, and examines where the field is headed.

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Compute Carriers: From 2.5D to 3.5D Integration

Large-die manufacturing runs up against a hard physical ceiling, the reticle size of the lithography tool, which caps the maximum area of any single chip. Meanwhile, demand for compute is scaling relentlessly. Heterogeneous integration design tackles this by projecting power the way a carrier strike group does: by assembling multiple chiplets through advanced packaging and vertical interconnects, breaking through the area bottleneck of a monolithic die.